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Digital Step Attenuator
15.5 dB, 0.5 dB Step 5 Bit, Parallel Control Interface, Dual Supply Voltage
Product Features * Dual supply voltage: VDD=+3V, VSS=-3V * Immune to latch up * Excellent accuracy, 0.1 dB Typ * Parallel control interface * Fast switching control frequency, 1MHz Typ * Low Insertion Loss * High IP3, +52 dBm typ * Very low DC power consumption * Excellent return loss, 20 dB Typ * Small size 4.0 x 4.0 mm Typical Applications * Base Station Infrastructure * Portable Wireless * CATV & DBS * MMDS & Wireless LAN * Wireless Local Loop * UNII & Hiper LAN * Power amplifier distortion canceling loops
75 DC-2000 MHz
DAT-15575-PN+ DAT-15575-PN
+ RoHS compliant in accordance with EU Directive (2002/95/EC)
The +Suffix identifies RoHS Compliance. See our web site for RoHS Compliance methodologies and qualifications.
General Description The DAT-15575-PN is a 75 RF digital step attenuator that offers an attenuation range up to 15.5 dB in 0.5 dB steps. The control is a 5-bit parallel interface, operating on dual supply voltage: VDD=+3V, VSS=-3V. The DAT-15575-PN is produced using a unique CMOS process on silicon, offering the performance of GaAs, with the advantages of conventional CMOS devices.
Simplified Schematic
RF Input
8dB
4dB
2dB
1dB
0.5dB
RF Out
Parallel Control Latch Enable
Control Logic Interface
REV. C M112685 DAT-15575-PN 071025 Page 1 of 12
Digital Step Attenuator
RF Electrical Specifications, DC-2000 MHz, TAMB=25C, VDD=+3V, VSS=-3V
Parameter Accuracy @ 0.5 dB Attenuation Setting Freq. Range (GHz) DC-1.2 1.2-2.0 DC-1.2 1.2-2.0 DC-1.2 1.2-2.0 DC-1.2 1.2-2.0 DC-1.2 1.2-2.0 DC-1.2 1.2-2.0 DC-2.0 DC-2.0 DC-1.2 1.2-2.0 Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. 0.03 0.05 0.03 0.1 0.07 0.15 0.05 0.15 0.1 0.24
1.2 1.6
DAT-15575-PN+ DAT-15575-PN
Max. 0.17 0.18 0.19 0.2 0.23 0.25 0.25 0.35 0.25 0.55
1.8 2.1
Units dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm -- --
Accuracy @ 1 dB Attenuation Setting
Accuracy @ 2 dB Attenuation Setting
Accuracy @ 4 dB Attenuation Setting
Accuracy @ 8 dB Attenuation Setting Insertion Loss(note1) @ all attenuator set to 0dB Input IP3(note 2) (at Min. and Max. Attenuation) Input Power @ 0.2dB Compression* (at Min. and Max. Attenuation) VSWR
+52 +24 1.6 1.7
-- -- 2.0 2.0
Notes: 1. I. Loss values are de-embedded from test board Loss (test board's Insertion Loss: 0.10dB @100MHz, 0.40dB @1200MHz, 0.55dB @2000MHz, 0.75dB @4000MHz) 2. Input IP3 and 1dB compression degrades below 1 MHz
DC Electrical Specifications
Parameter VDD, Supply Voltage VSS, Supply Voltage IDD (ISS), Supply Current Control Input Low Control Input High Control Current Min. 2.7 -3.3 -- -- 0.7xVDD -- Typ. 3 -3 -- -- -- -- Max. 3.3 -2.7 100 0.3xVDD -- 1 Units V V A V V A
Switching Specifications
Parameter Switching Speed, 50% Control to 0.5dB of Attenuation Value Switching Control Frequency Min. -- -- Typ. 1.0 1.0 Max. -- -- Units Sec MHz
Absolute Maximum Ratings
Parameter Operating Temperature Storage Temperature VDD VSS Voltage on any input ESD, HBM ESD, MM Input Power Ratings -40C to 85C -55C to 100C -0.3V Min., 4V Max. -4V Min., 0.3V Max. -0.3V Min., VDD+0.3V Max. 500V 100V +24dBm
Page 2 of 12
Digital Step Attenuator
Pin Description
Function N/C RF in N/C GND LE VDD N/C PUP2 VDD GND GND VSS GND RF out C8 C4 C2 GND C1 C0.5 GND Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Paddle Description
DAT-15575-PN+ DAT-15575-PN
Pin Configuration (Top View)
C2
17
RF in port (Note 1) Not connected (Note 3) Ground connection Latch Enable Input (Note 2) Positive Supply Voltage Not connected Power up selection bit Positive Supply Voltage Ground connection Ground connection Negative supply voltage Ground connection RF out port (Note 1) Control for attenuation bit, 8 dB Control for attenuation bit, 4 dB Control for attenuation bit, 2 dB Ground Connection Control for attenuation bit, 1 dB Control for attenuation bit, 0.5 dB Paddle ground (Note 4)
C1
N/C RFin N/C GND LE
20
19
18
16
C4
Not connected (Note 3)
GND
C0.5
1
15
C8 RFout GND VSS GND
2 3
4 5
2x2mm Paddle ground
10
6 7
14
13 12
11
8
VDD
9
Notes: 1. Both RF ports must be held at 0VDC or DC blocked with an external series capacitor. 2. Latch Enable (LE) has an internal 100K resistor to VDD. 3. Place a shunt 10K resistor to GND. 4. The exposed solder pad on the bottom of the package (See Pin Configuration) must be grounded for proper device operation.
PUP2
GND
VDD
N/C
page 3 of 12
Digital Step Attenuator
Typical Performance Curves
7 6
DAT-15575-PN+ DAT-15575-PN
1 0.9
INSERTION LOSS (Ref) @ +25C, +85C, -45C
ATTENUATION (0.5dB) @ +25C,+85C,-45C
-45C +25C +85C
+85C
5 4 3 2 1 0 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
0.8 0.7 0.6
(dB)
+25C
-45C
(dB)
0.5 0.4 0.3 0.2 0.1 0 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
ATTENUATION (1dB) @ +25C,+85C,-45C
1.5 1.4 1.3 1.2
(dB)
ATTENUATION (2dB) @ +25C,+85C,-45C
3 2.8 2.6 2.4 2.2
-45C +25C +85C
-45C +25C +85C
1.1 1 0.9 0.8 0.7 0.6 0.5 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
(dB)
2
1.8 1.6 1.4 1.2 1 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
5 4.8 4.6 4.4
ATTENUATION (4dB) @ +25C,+85C,-45C
8.8
-45C +25C +85C
ATTENUATION (8dB) @ +25C,+85C,-45C
-45C +25C +85C
8.6 8.4 8.2
(dB)
(dB)
4.2 4 3.8 3.6 3.4 3.2 3 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
8 7.8 7.6 7.4 7.2 7 6.8 6.6 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
Page 4 of 12
Digital Step Attenuator
Typical Performance Curves
18 17
(dB)
DAT-15575-PN+ DAT-15575-PN
ATTENUATION (15.5dB) @ +25C,+85C,-45C
-45C +25C +85C
16 15 14 13 12 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
50
RETURN LOSS IN S11 (Ref) @ +25C,+85C,-45C
50
RETURN LOSS OUT S22 (Ref) @ +25C,+85C,-45C
40
-45C +25C +85C
40
-45C +25C +85C
30
(dB)
30
(dB)
20
20
10
10
0 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
0 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
50
RETURN LOSS IN S11 (Major Attenuation Steps) @ +25C
ATT=0dB ATT=1dB ATT=4dB ATT=15.5dB ATT=0.5dB ATT=2dB ATT=8dB
RETURN LOSS OUT S22 (Major Attenuation Steps) @ +25C
50 ATT=0dB ATT=1dB ATT=4dB ATT=15.5dB ATT=0.5dB ATT=2dB ATT=8dB
40
40
(dB)
30
30
20
10
0 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
(dB)
20 10 0 0 500 1000 1500 Frequency (MHz) 2000 2500 3000
Page 5 of 12
Digital Step Attenuator
Typical Performance Curves
IP-3 INPUT (Major Attenuation Steps) @ +25C
70 60 50
(dBm)
DAT-15575-PN+ DAT-15575-PN
IP-3 INPUT (Major Attenuation Steps) @ +85C
70 60 50 40 30 20 10 0
30 20 10 0 0
ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=15.5dB
(dBm)
40
ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=15.5dB
200
400
600
800
1000
1200
1400
1600
1800
2000
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Frequency (MHz)
Frequency (MHz)
IP-3 INPUT (Major Attenuation Steps) @ -45C
70 60
0.2
COMPRESSION @INPUT POWER=+24dBm (+25C)
0
50
(dBm)
(dB)
40 30 20 10 0 0
-0.2
ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=15.5dB
-0.4
-0.6
ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=15.5dB 0 200 400 600 800 1000 1200 1400 1600 1800 2000
-0.8
200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (MHz)
Frequency (MHz)
0.2
COMPRESSION @INPUT POWER=+24dBm (+85C)
0.2
COMPRESSION @INPUT POWER=+24dBm (-45C)
0
0
-0.2
(dB)
-0.2
-0.4
-0.6
ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=15.5dB 0 200 400 600 800 1000 1200 1400 1600 1800 2000
(dB)
-0.4
-0.6
ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=15.5dB
-0.8 Frequency (MHz)
-0.8 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (MHz)
Page 6 of 12
Digital Step Attenuator
Outline Drawing (DG983-1)
PCB Land Pattern
DAT-15575-PN+ DAT-15575-PN
Suggested Layout, Tolerance to be within .002
Device Marking
15575
Outline Dimensions (inch ) mm
A
B .157 4.00
C .035 0.90
D .008 0.20
E .081 2.06
F .081 2.06
G .010 0.25
H -- --
J .022 0.56
K .020 0.50
L .166 4.22
M .166 4.22
N .070 1.78
P .012 0.31
Q .026 0.66
R .070 1.78
WT. GRAMS .04
.157 4.00
page 7 of 12
Digital Step Attenuator
Suggested Layout for PCB Design (PL-200)
DAT-15575-PN+ DAT-15575-PN
The suggested Layout shows only the footprint area of the DAT, and the components located near this area (i.e.: R1, R7). For the complete Layout, see photo and schematic diagram on page 11 of 12.
NOTES: 1. TRACE WIDTH IS SHOWN FOR FR4 WITH DIELECTRIC THICKNESS. .025" .002". COPPER: 1/2 OZ. EACH SIDE. FOR OTHER MATERIALS TRACE WIDTH MAY NEED TO BE MODIFIED. 2. 0603, 0402 SIZE CHIP FOOT PRINTS SHOWN FOR REFERENCE, VALUES OF RESISTORS WILL VARY BASED ON APPLICATION. 3. BOTTOM SIDE OF THE PCB IS CONTINUOUS GROUND PLANE. DENOTES PCB COPPER LAYOUT WITH SMOBC (SOLDER MASK OVER BARE COPPER) DENOTES COPPER LAND PATTERN FREE OF SOLDERMASK
Page 8 of 12
Digital Step Attenuator
Simplified Schematic
RF Input
8dB 4dB 2dB 1dB 0.5dB
DAT-15575-PN+ DAT-15575-PN
RF Out
Parallel Control Latch Enable
Control Logic Interface
The DAT-15575-PN parallel interface consists of 5 control bits that select the desired attenuation state, as shown in Table 1: Truth Table
Table 1. Truth Table
Attenuation State
Reference 0.5 (dB) 1 (dB) 2 (dB) 4 (dB) 8 (dB) 15.5 (dB)
C8
0 0 0 0 0 1 1
C4
0 0 0 0 1 0 1
C2
0 0 0 1 0 0 1
C1
0 0 1 0 0 0 1
C0.5
0 1 0 0 0 0 1
Note: Not all 32 possible combinations of C0.5 - C8 are shown in table
The parallel interface timing requirements are defined by Figure 1 (Parallel Interface Timing Diagram) and Table 2 (Parallel Interface AC Characteristics), and switching speed. For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenunation state control values, then pulse LE HIGH to LOW (per Figure 1) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers).
Figure 1: Parallel Interface Timing Diagram
LE
Table 2. Parallel Interface AC Characteristics
Symbol Parameter
LE minimum pulse width data set-up time before clock rising edge of LE data hold time after clock falling edge of LE
Min.
30 10 10
Max.
Units
ns ns ns
tLEPW tPDSUP
Parallel Data C8:C0.5
tPDHLD
tPDSUP
tLEPW
tPDHLD
page 9 of 12
Digital Step Attenuator
DAT-15575-PN+ DAT-15575-PN
Pin 1 must always be low to prevent the attenuator from entering an unknown state. Power-up Control Settings The DAT-15575-PN always assumes a specifiable attenuation setting on power-up, allowing a known attenuation state to be established before an initial parallel control word is provided. When the attenuator powers up with LE=0, the control bits are automatically set to one of two possible values. These two values are selected by the power-up control bit, PUP2, as shown in Table 3: (Power-Up Truth Table, Parallel Mode).
Table 3. Power-Up Truth Table, Parallel Mode
Attenuation State
Reference 8 (dB) Defined by C0.5-C8 (See Table 1-Truth Table)
PUP2
0 1 X (Note 1)
LE
0 0 1
Note 1: PUP2 Connection may be 0, 1, GROUND, or not connect, without effect on attenuation state.
Power-Up with LE=1 provides normal parallel operation with C0.5-C8, and PUP2 is not active.
Page 10 of 12
Digital Step Attenuator
TB-341 Evaluation Board Schematic Diagram
1 2 3 4 5 6 7 8
DAT-15575-PN+ DAT-15575-PN
GND
1
2
GND
VDD
13
12
11
10
9
C2
8
C4
C8
GND
C16
C0.5
C1
DC SUPPLY J2.2
PARALLEL CONTROL J1.1
13
12
11
10
9
8
14
IC1
2 3 4 5 6
7
14 7
IC2
2 3 4 5 6
7
1
+ C1
1
C2
C4 C3 C5 C6 R4 C7 R5 C8
R1
R2
R3
R6
C0.5
GND
C1
C2
17
20
19
18
RFin
R9
N/C RFin
C4
16 15 14
1 2
C8 RFout
3
R7
N/C
4
DAT
RFout
C12
13
GND
GND
12
1
2
C9
LE
Vss
5 6 7 8 9 11 10
+
GND
GND
PUP2
N/C
VDD
LE
2 1
R8
GND
VDD
C13
IC3
5
6
C11
R10
R11
+
C10
1
2
3
4
GND
VDD
Bill of Materials R1 - R8 R10, R11 R9 C1, C11 & C12 IC1, IC2 IC3 Resistor 0603 10 KOhm +/- 1% Resistor 0603 470 Ohm +/- 1% Resistor 0402 10 KOhm +/- 1% Tantalum Capacitor 100nF +/- 10% Hex inverting Schmitt trigger MM74HC14 Dual non-inverting Schmitt trigger SN74LVC2G17
C2 - C10 & C13 NPO Capacitor 0603 100pF +/- 5%
GND
Vss
LE CONTROL J1.2
DC SUPPLY J2.1
TB-341
page 11 of 12
Digital Step Attenuator
Tape and Reel Packaging Information Table T&R
TR No.
No. of Devices Designation Letter
T
DAT-15575-PN+ DAT-15575-PN
Reel Size
Tape Width
Pitch
Unit Orientation
3000
T-005 multiples of 10, less than full reel of 3K
multiples of 10, on tape only
13 inch
12 mm 8 mm
Direction of Feed
Tape Cavity
PR
13 inch
E
not applicable
Ordering Information
Model No. Description
Parallel Interface, Dual Voltage (Negative and Positive)
Test Board Only
Packaging Designation Letter (See Table T&R)
E
Quantity Min. No. of Units
10
Price $ Ea.
$3.55
DAT-15575-PN (+)
TB-341
Not Applicable
1
$79.95
How to Order
Example: 3000 pieces of DAT-15575-PN+ 3K DAT-15575-PN+
T&R=T
Quantity
Model No.
T&R designation letter (see Table T&R)
Page 12 of 12

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